1) Field of the Invention
The present invention relates to a carrier regenerating circuit suitable for a demodulator used in a receiving-side radio equipment included in a radio communications system, and particularly for a demodulator that demodulates many-valued orthogonal amplitude modulation signals.
2) Description of the Related Art
FIG. 12 is a block diagram showing the configuration of receiving-side radio equipment in a radio system. Referring to FIG. 12, a demodulator (carrier regenerating circuit) 70 consists of an orthogonal detecting circuit 40 having a voltage-controlled oscillator (VCO) 46, an analog/digital (A/D) converting circuit 41, a phase error detecting circuit 42, a first digital/analog (D/A) converting circuit 43, a low-pass filter 44, an operational amplifier 45, a sweep generating source (low-frequency oscillator) 47, a second digital/analog (DIA) converting circuit 48, a low-pass filter 49, and a digital signal processing section 50.
The demodulator 70 shown in FIG. 12 employs a many-valued orthogonal amplitude-demodulation (many-valued QAM: Quadrature Amplitude Modulation) system.
The orthogonal detecting circuit 40 branches an input IF-band QAM signal (hereinafter, often referred merely to as an input signal) in two, and mixes (multiplies) the two branched input signals by two regenerated carrier signals supplied from the voltage-controlled oscillator 46, perpendicular to each other in phase, so that two kinds of baseband signals [I-channel (Ich) and Q-channel (Qch) signals] perpendicular to each other are obtained by orthogonally detecting the input signal.
The A/D converting circuit 41 converts each of baseband signals (analog signals) from the orthogonal detection circuit 40 into a digital signal, for example, of 8 bits (i7 to i0 and q7 to q0). The phase error detecting circuit 42 detects a phase error of a QAM signal output via the A/D converting circuit 41. In this case, the phase error detecting circuit 42 detects the phase error signal in an input signal based on the Ich polarity signal (polarity bit: i.sub.7) representing the rotational direction of the signal point of the input signal and the Qch error signal (error bit: q.sub.5) representing the rotational rate of the signal point. In contrast, the phase error signal may be detected based on the Qch polarity signal and the Ich error signal.
The first D/A converter 43 converts phase error information as digital information from the phase error detecting circuit 42 into an analog form. The low-pass filter 44 receives the digital information from the phase error detecting circuit 42 via the first D/A converting circuit 43 and then outputs a voltage control signal to the voltage controlled oscillator 46.
That is, in the demodulator 70, the input signal is synchronously detected by means of the PLL (Phase Locked Loop) circuit formed of the phase error detecting circuit 42, the first D/A converting circuit 43 and the low-pass filter 44.
The operational amplifier 45 controls the voltage controlled oscillator 46 in the orthogonal detecting circuit 40 by adjusting the direct current (DC) voltage from the low-pass filter 44 or 49 based on the reference voltage Ref, thus optimizing the DC voltage according to variations (performance errors) of the voltage controlled oscillator 46. A variable resistor (not shown) which varies the reference voltage Ref is connected to the operational amplifier 45.
The digital signal processing section 50 subjects a digital signal from the A/D converting circuit 41 to a desired compensating process such as amplitude equalizing process. Specifically, the digital signal processing section 50 outputs a frame alarm signal (FALM) when the input signal is completely out of synchronization.
Further, in order to execute a sweep operation, the sweep generating source 47 hunts a synchronous frequency of an input signal by supplying a ultra low frequency signal to the voltage controlled oscillator 46 based on the frame alarm signal from the digital signal processing unit 50. When the synchronization of the input signal is established, the sweep operation halts.
The second D/A converting circuit 48 converts the ultra low frequency signal (digital signal) output from the sweep generating source 47 into an analog signal. When receiving the signal from the sweep generating source 47 via the second D/A converting circuit 48, the low-pass filter 49 outputs it to the voltage controlled oscillator 46.
In the demodulator 70 with the above-mentioned arrangement, the orthogonal detecting circuit 40 orthogonally detects a QAM signal received, based on a regenerated carrier signal supplied from the voltage controlled oscillator 46 and then converts it into an Ich baseband signal and a Qch baseband signal. Then the A/D converting circuit 41 converts the Ich baseband signal and the Qch baseband signal into respective digital signals. The digital signal processing unit 50 subjects the respective digital signals to a desired compensating process to output demodulated signals.
The phase error detecting circuit 42 detects the phase error signal of an input signal based on the I-channel polarity bit i7 and the Q-channel signal error bit q5. The first D/A converting circuit 43 converts the detected phase error signal into an analog signal and then outputs it as phase control information to the voltage controlled oscillator 46 via the low-pass filter 44.
In such an arrangement, the voltage controlled oscillator 46 can supply regenerated carrier signals in synchronous with the input signal by adjusting the oscillating frequency according to the phase error signal detected by the phase error detecting circuit 42. Hence, the AID converting circuit 41 can always execute an A/D converting process at the optimum timing (phase).
However, when the input signal is actually modulated according to the many-valued QAM modulation system such as a 64-value, 128-value, 256 value, or 512-value QAM modulation system, the above-mentioned PLL circuit (carrier reproducing loop) cannot provide its sufficient capture range (or the difference between a send frequency and a receive frequency) (less than 1/10, compared with the 16-value QAM modulation system). Hence the sweep operation is performed using the sweep generator 47 shown in FIG. 12. That is, even if the input signal is completely out of synchronization, the input signal can be certainly synchronized by executing a frequency sweeping operation by means of the sweep generator 47.
However, in the demodulator 70 shown in FIG. 12, previous adjustment must be made using a variable resistor to tolerate the variation in characteristic of the voltage controlled oscillator 46. Further, when the input signal is completely out of synchronization, the sweep operation is performed using a ultra low frequency from the sweep generator (low-frequency oscillator) 47. However, it takes much time to reestablish the normal synchronization. That is, the problem is that the pulling operation is largely delayed.
When synchronization is reestablished, the sweep operation of the sweep generating source is interrupted. However, the difference between the free run at the point of time of the interruption (the frequency of a free-oscillated signal by the voltage-controlled oscillator 46 without any phase synchronization) and the local frequency of the transmission signal (IF signal) accounts for a steady-state phase error. Thus as the value of the many-valued modulation increases (e.g. 64-value or more), the steady-state phase error cannot be ignored. As a result, the error is shown as degradation in error rate when the signals are generated at the rear stage of the demodulator.